[HPGMG Forum] HPGMG release v0.1

Vitali A. Morozov morozov at anl.gov
Mon Jun 9 16:29:17 UTC 2014


On 06/09/2014 11:19 AM, Jed Brown wrote:
> "Vitali A. Morozov" <morozov at anl.gov> writes:
>> and see that you provide STREAM-based memory bandwidth for some
>> architectures. I suggest to specify a particular benchmark, let us say
>> "triad", because the result of STREAM is benchmark-dependent.
> Yes, I would prefer Triad.
>
>> For BG/Q, I have measured 29.3 GB/s/node on "triad". For Cray XC30, I
>> have measured 48.6 GB/s/socket or 97.1 GB/s/node. This is slightly
>> better than the numbers you have reported.
> I'll update the BG/Q number.  What code is needed to observe this?  (I
> think I've always heard 26-27 GB/s quoted and have not personally
> measured higher.)  It would be helpful to list this somewhere on the
> ALCF website.

We normally advertise 18.3 B per cycle number, which is 29.28 GB/s to be 
exact. Our "acceptance" run has shown 28.6. Anyway, the difference is tiny.

>
>
> I assume that your 97 GB/s on XC30 using E5-2697v2?  The numbers I used
> come from this page which quotes STREAM Triad at 89 GB/s.
>
>    http://www.nersc.gov/users/computational-systems/edison/configuration/
>
>> For Cray XC30, the flop rate is 518.4 GF per node. For Xeon E5-2697 v2 @
>> 2.7 GHz,
> Edison uses E5-2695v2 (2.4 GHz), thus the somewhat lower number.

Agree. Sorry.

Vitali



>
>> each core can have 8 Flops/cycle - 4 way FMA - or 8 * 2.7 = 21.6
>> GFlops per core. 12 cores result in 259.2 GFlops per socket, 2 sockets
>> give 518.4 GFlops.



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